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Wednesday, June 16, 1999
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08:30
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Registration
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09:00
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Welcoming Remarks (Vijay Jain,
Klaus
D. Müller-Glaser)
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09:30
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Keynote Speech
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10:15
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Break
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10:30
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Session 1: Communication and Distributed Systems
(Session Chair: Fabrice Kordon)
- Rapid Prototyping of Formally Modelled Distributed Systems (Buchs,
D.; Buffo, M.)
- System Design Validation using Formal Models (Henderson, P.; Walters,
R.)
- Communication Interface Synthesis for Multilanguage Specifications
(Hessel, F.; Coste, P.;
LeMarrec, P.; Zergaonoh, N.; Daveau, J.; Jerraya, A.)
- Development of Reusable E1 Tranceiver Suitable for Rapid Prototyping
(Vasilliou, A.; Gounaris, K.; Adaos, K.; Mitsainas, D.; Alexiou,
G.; Nikolos, D.)
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12:15
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Lunch
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14:00
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Session 2: Reconfigurable Architectures
(Session Chair: David Landis)
- First Steps towards a Reconfigurable Asynchronous System (Erhard,
W.; Reinsch, A.; Schober,
T.)
- Rapid System Prototyping for High Performance Reconfigurable Computing
(Shrivastava, S.; Jain, V.)
- 3-D Floorplanning: Simulated Annealing and Greedy Placement Methods
for Reconfigurable Computing Systems (Bazargan,
K.; Kastner, R.; Sarrafzadeh, M.)
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15:15
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Break
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15:45
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Session 3: Reuse
(Session Chair: Didier Buchs)
- A Design and Tool Reuse Methodology for Rapid Prototyping of Application
Specific Instruction Set Processors (Kim,
Y.; Kim, T.)
- Language-Based Rapid Prototyping Methods for Legacy System Re-Engineering
and Re-Use (Landis, D.; Guddeti,
P.; Hulina, P.; Coraor, L.)
Session 4: Formal Methods
(Session Chair: Didier Buchs)
- Rapid Prototyping of Specification Language Implementations (Leucker,
M.; Noll, T.)
- A Methodological Approach to Implement CSP on FPGA (Habbas,
Z.; Herrmann, F.; Krajecki, M.; Singer, D.)
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17:30
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Daily Wrap Up
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18.00
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Break
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19:30
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Social Event
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Thursday, June 17, 1999
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08:30
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Session 5: Case Studies
(Session Chair: Manfred
Glesner)
- ATM Traffic Management Systems: ASIC Fast Prototyping (Buzzoni,
M.; Cardini, D.; Gallino, R.; Romagnese,
R.)
- Transformations of a 3D Image Reconstruction Algorithm for Data
Transfer and Storage Optimisation (Van
Achteren, T.; Adé,
M.; Lauwereins,
R.; Proesmans, M.; Van Gool, L.; Bormans, J.; Catthoor, F.)
- Fast Prototyping: A Case Study - The JPEG Compression Algorithm
(Pillement, S.; Torres, L.;
Robert, M.; Cambon, G.)
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09:45
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Break
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10:00
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Session 6: Special Session "Rapid Prototyping
of Embedded Systems with Hard Time Constraints"
(Session Chair: Rolf Ernst)
Introduction (Ernst, R.)
- Process Versions in Rapid Prototyping (Österling,
A.; Ernst, R.)
- The REAR Framework for Emulation and Analysis of Embedded Hard Real-Time
Systems (Petters, S.; Muth,
A.; Kolloch, T.; Hopfner, T.; Fischer, F.; Färber, G.)
- Communication Performance Models for Architecture-precise Prototyping
of Real-time Embedded Systems (Renner,
F.; Becker,
J.; Glesner, M.)
- Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping
(Bringmann, O.; Rosenstiel,
W.; Muth,
A.; Färber, G.; Slomka, F.; Hofmann, R.)
- A Scalable Hardware Library for the Rapid Prototyping of SDL Specifications
(Dörfel,
M.; Slomka, F.; Hofmann, R.)
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12:20
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Lunch
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14:00
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Keynote Speech
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14:45
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Break
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15:00
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Session 7: Partitioning, Scheduling and Performance
Analysis
(Session Chair: Rudy
Lauwereins)
- FPGA Partitioning for Rapid Prototyping: A 1 Million Gate Design
Case Study (Krupnova,
H.; Rabedaoro, C.; Saucier, G.)
- An Iterative Algorithm for Partitioning and Scheduling of Area Conctrained
HW-SW Systems (Chatha, K.;
Vemuri, R.)
- Scheduling Strategies and Estimations for Concept-Oriented Rapid
Prototyping (Burst,
A.; Wolff, M.;
Kühl, M.;
Müller-Glaser,
K.)
- Performance Analysis of Real-Time Operating Systems by Emulation
of an Embedded System (Weiss, K.;
Steckstor, T.; Rosenstiel, W.)
Session 8: Overview and Comparison
(Session Chair: Rudy
Lauwereins)
- System-Level Verification - a Comparison of Approaches (Turner,
R.)
- A Case Study: Logic Emulation - Pitfalls and Solutions (Harbich,
K.; Stohmann, J.; Barke, E.; Schwoerer, L.)
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17:30
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Daily Wrap Up
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18:00
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Break
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19:30
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Social Event
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Friday, June 18, 1999
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08:30
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Keynote Speech
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09:15
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Break
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09:30
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Session 9: Design Methodologies
(Session Chair: Klaus
D. Müller-Glaser)
- System Level Virtual Prototyping of DSP ASICs Using Grammar Based
Approach (Hemani, A.; Öberg,
J.; Deb, A.)
- An Integrated Development Environment Prototyping Safety Critical
Systems (Thompson, J.; Heimdahl,
M.)
- A Rapid Modeling Tool for Virtual Prototyping (Cyre,
W.; Hess, J.; Gunawan, A.; Sojitra, R.)
- Graphical Design of Embedded Control System Software based on SDL/RealTime
with Special Support for Safety Critical Applications (Welge,
R.; Müller-Schloer, C.)
- Model Based Multi-Level Prototyping (Bredenfeld,
A.; Wilberg, J.)
- Extended Synchronous Dataflow for Efficient DSP System Prototyping
(Park, C.; Chung, J.; Ha,
S.)
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12:10
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Lunch
(Steering Committee Meeting)
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14:00
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Session 10: Interface Technologies
(Session Chair: Klaus
Buchenrieder)
- Interface Technologies for Versatile Rapid-Prototyping Systems (Spitzer,
B.; Burst, A.;
Müller-Glaser,
K.)
- Field Programmable Multi Chip Modules using Programmable Laser Interconnects
(Pasham, V.; Moreno, W.; Falquez,
F.)
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14:50
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Break
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15:05
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Session 11: Re-Engineering Technologies
(Session Chair: Marc Engels)
- Architectural Re-engineering of Janus using Object Modeling and
Rapid Prototyping (Shing,
M.; Luqi; Berzins, V.; Saluto, M.; Williams, J.)
- A Rapid Prototyping Methodology for Reverse Engineering of Legacy
Electronic Systems (Landis, D.;
Deno, S.)
Session 12: FPGA-based design
(Session Chair: Marc Engels)
- A Universal Module Generator for LUT-Based FPGAs (Abke,
J.; Stohmann, J.; Barke, E.)
- Incremental Compilation for Logic Emulation (Tessier,
R.)
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16:45
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Daily Wrap Up and Closing Session
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17:30
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End of RSP'99
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