Presentation kit
(for authors)
Program at a glance
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Wednesday June 8 |
Thursday June 9 |
Friday June 10 |
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08:00 |
Registration |
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08:10 |
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08:20 |
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08:30 |
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Session
8
Processor Design and Prototyping |
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08:40 |
Opening
Session |
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08:50 |
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09:00 |
Keynote
Address |
Session
4
FPGAs for Prototyping |
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09:10 |
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09:20 |
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09:30 |
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09:40 |
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09:50 |
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10:00 |
Break |
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10:10 |
Break |
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10:20 |
Session
1
Network and Protocols |
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10:30 |
Session
9
Testing Issues in Prototyping |
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10:40 |
Break |
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10:50 |
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11:00 |
Session
5
Software Design and Prototping |
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11:10 |
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11:20 |
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11:30 |
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11:40 |
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11:50 |
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12:00 |
Lunch |
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12:10 |
Lunch |
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12:20 |
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12:30 |
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12:40 |
Lunch |
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12:50 |
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13:00 |
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13:10 |
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13:20 |
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13:30 |
Session
2
Tools for Rapid Prototyping |
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13:40 |
Session
10
Co-Design II |
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13:50 |
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14:00 |
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14:10 |
Session
6
Applications |
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14:20 |
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14:30 |
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14:40 |
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14:50 |
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15:00 |
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15:10 |
Break |
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15:20 |
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15:30 |
Session
3
Co-Design I |
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15:40 |
Closing
Session |
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15:50 |
Break |
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16:00 |
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16:10 |
Session
7
Hardware Prototyping |
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16:20 |
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16:30 |
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16:40 |
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16:50 |
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17:00 |
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17:10 |
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17:20 |
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17:30 |
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17:40 |
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17:50 |
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18:00 |
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18:10 |
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18:20 |
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18:30 |
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Conference
Banquet |
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18:40 |
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18:50 |
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19:00 |
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19:10 |
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19:20 |
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19:30 |
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19:40 |
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19:50 |
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20:00 |
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20:10 |
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20:20 |
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20:30 |
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20:40 |
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20:50 |
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21:00 |
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21:10 |
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21:20 |
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21:30 |
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21:40 |
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21:50 |
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22:00 |
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Detailed program
Tuesday June 7th
Wednesday June 8th
| 8:00 |
Registration |
| 8:40 |
Welcome |
| 9:00 |
Keynote Address
Parallel SoC platforms: Trends, Objectives & Solutions
Dr. Paulin, Director of SoC Platform Automation, Advanced
System Technology of STMicroelectronics (Canada) Inc.
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| 10:00 |
Break |
| 10:20 |
Session
1: Networks and Protocols (chair: B. Michael, Naval
Postgraduate School)
Synthesis of Communication Structures and Protocols
in Distributed Embedded Systems
S. Ihmor, T. Loke (University of Paderborn), W. Hardt (Chemnitz
University of Technology)
Heterogeneous modelling of an Optical Network-on-Chip
with SystemC
M. Brière, E. Drouard, F. Mieyeville, D. Navarro,
I. O'Connor (Ecole Centrale de Lyon - France)
Models for Embedded Application Mapping onto NoCs:
Timing Analysis
C. Marcon (UFRGS/PUCRS), M. Kreutz, N. Calazans (UFRGS),
A. Susin (PUCRS)
Performance Evaluation of a NoC-Based Design for
MC-CDMA Telecommunications using NS-2
R. Lemaire, F. Clermidy, Y. Durand, D. Lattard, (CEA-LETI),
A. Jerraya (TIMA Laboratory)
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| 12:00 |
Lunch |
| 14:00 |
Session 2: Tools
for Rapid Prototyping (chair: M. Shing, Naval Postgraduate
School)
Leveraging Model Representations for System Level
Design Tools
J. Lapalme, E. Aboulhamid (Université de Montréal),
G. Nicolescu (Ecole Polytechnique de Montréal)
Porting DSP Applications Across Design Tools Using
the Dataflow Interchange Format
C. Hsu, S. Bhattacharyya (University of Maryland, College
Park)
Automatic Generation of component wrappers by Composition
of HW Library elements Starting from Communication Service
Specification
A. Grasset, F. Rousseau, A. Jerraya (TIMA Laboratory)
High Level Synthesis for Data-Driven Applications
Bergeron, Saint-Mleux, Feeley, David (Université
de Montréal)
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| 15:40 |
Break |
| 16:00 |
Session 3: Co-Design
I (work in progress session, chair: K.Kent, New Brunswick
Univ.)
An Open Source Based Integrated Framework for Functional
Verification of System On Chip
S. Park, S. Chae (Seoul National University)
Design exploration and HW/SW rapid prototyping
for real-time system design
Huet, Casseau (Lester) Pasquier (IREENA)
An Approach for Functional Decomposition Applied
to State-Based Designs
L. Demoracski, D. Avresky (Northeastern University)
Communication Primitives Driven Hardware Design
and Test Methodology Applied on Complex Video Applications
A. Chirila-Rus, K. Denolf (IMEC)
Thread-Level Parallel Execution in Co-designed
Virtual Machines
T. Hall, K. Kent (University of New Brunswick)
A HyperTransport Chip-to-Chip Interconnect Tunnel Developed Using SystemC
A. Castonguay and Y. Savaria
Prototyping a Residential Gateway Using Xilinx ISE
S. W. Song, J. D. Zheng, and W. B. Gardner
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| 17:40 |
End of sessions for day I |
Thursday June 9th
| 9:00 |
Session 4: FPGAs for Rapid
Prototyping (chair: K. Mueller-Glaser,
Univ. Karlsruhe)
Prototyping Globally Asynchronous Locally Synchronous
Circuits on Commercial Synchronous FPGAs
M. Najibi. K. Saleh, M. Naderi, H. Pedram (Amirkabir University
of Technology)
Dynamic Reconfiguration of IP based Systems
M. Visarius, A. Meisel, M. Schelthauer, W. Hardt (Chemnitz
University)
Straight Method for Reallocation of Complex Cores
by Dynamic Reconfiguration in Virtex II FPGAs
Y. Krasteva, A. Jimeno, E. de la Torre, T. Riesgo
(Universidad Politécnica de Madrid)
A practical approach for circuit routing on dynamic
reconfigurable devices
A. Ahmadinia, C. Bobda, M. Majer, J. Teich (University of
Erlangen-Nuremberg), S. Fekete, J. van der Veen (Braunschweig
University of Technology)
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| 10:40 |
Break |
| 11:00 |
Session 5: Software Design
and Prototyping (chair: F. kordon,
Univ. P. & M. Curie)
Simulation for Resolution of CS problem for Multiple
Common Variables using Multiprocessor Environment
G. Qader, M.Y. Javid (National University of Science &
Technology, PAKISTAN)
Rapid Prototyping of Embedded Software Using Selective
Formalism
J. Carter, M. Xu, W. Gardener (University of Guelph)
Test-time, Run-time, and Simulation-time Temporal
Assertions in RSP
D. Drusinski, K. Demir, M.T. Shing (Naval Postgraduate School)
Rapid Development of Customized Middleware
Th.Vergnaud, J. Hugues, L. Pautet (ENST-Paris), F. Kordon
(LIP6 - Paris)
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| 12:40 |
Lunch |
| 14:10 |
Session 6: Applications
(chair: L. Pautet, Telecom Paris)
An 8 GHz Ultra-Wide Band Transceiver Prototyping
Testbed
D. Agarwal, C. Anderson, P. Athanas (Virginia Tech)
Enabling a Real-Time Solution for Neuron Detection
with Reconfigurable Hardware
B. Cordes, J. Dy, M. Leeser (Northeastern University)
COMPASS ˆ A novel Concept of a Reconfigurable
Platform for Automotive System Development and Test
C. Bleser, K. Mueller-Glaser (University of Kalrsruhe)
Allocation for Real-Time Video Processing on FPGA
B. Thomberg, L. Olsson, M. O'Nils (Mid-Sweden University)
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| 15:50 |
Break |
| 16:10 |
Session 7: Hardware
Prototyping (work in progress session, chair: P. Athanas,
Virginia Tech)
Accelerating a Multiprocessor Reconfigurable Architecture
with Pipelined VLIW Units
A. Azevedo, S. Bampi, F. Wagner (UFRGS), R. Soares, I. Silva
(UFRN)
Residential Gateway Rapid Prototype
A. Castonguay, Y. Savaria (École Polytechnique de
Montréal)
SyCE: An Integrated Environment for System Design
in SystemC
R. Drechsler, G. Fey, C. Genz (University of Bremen)
KoVer : A sophisticated residue arithmetic generator
N. Kostaras, H. Vergos (University of Patras)
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| 17:10 |
End of sessions for day II |
| 18:30 |
Conference Banquet |
Friday June 10th
| 8:30 |
Session 8: Processor Design
and Prototyping (chair: W. Hardt, Univ. Chemnitz)
Custom Instruction filter Cache Synthesis for Low-Power
Embedded Systems
K. Vivekanandarajah, T. Srikanthan (Centre for High Performance
Embedded Systems, Singapore)
Performance Improvement of Multiprocessor Simulation
by Optimizing Synchronization and Communication
M. Chung, C. Kyung (Korea Advanced Institute of Science
and Technology)
Optimization Techniques for ADL-driven RTL Processor
Synthesis
O. Schliebusch, A. Chattopadhyay, E. Witte, D. Kammler (ISS,
RWTH-Aachen)
Automated Floating-point to Fixed-point Conversion
with the fixify Environment
P. Belanovic, M. Rupp (Vienna University of Technology)
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| 10:10 |
Break |
| 10:30 |
Session 9: Testing
Issues in Prototyping (chair: D. Buchs, Univ. geneva)
Discrete-Continuous Simulation Model for Accurate
Validation in Component-Based Design of Heterogeneous SoC
F. Bouchhima, G. Nicolescu (Ecole Polytechnique de Montreal),
M. Aboulhamid (Universite de Montreal) , M. Abid (Ecole
Nationale d'Ingenieurs de Sfax)
Test Automation and Safety Assessment in Rapid
Systems Prototyping
M. Auguston, B. Michael, M.T. Shing (Naval Postgraduate
School)
A Test Language for CO-OPN Specifications
L. Lucio, L. Pedro, D. Buchs (University of Geneva)
On the Use of Rewriting Logic for Verification
of Distributed Software Architecture Description based LfP
C.Jerad (ENIT,Tunis) K.Barkaoui (CEDRIC-CNAM, Paris)
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| 12:10 |
Lunch |
| 14:00 |
Session 10: Co-Design
II (chair: G. Nicolescu, Ecole Polytechnique
de Montréal)
The Ordering of Events in a Prototyping Platform
S. Dragone (IBM Research GmbH), C. Lombriser (Swiss Federal
Institute of Technology Zurich)
Systematic Design Flow for fast Hardware/Software
Prototype Generation from Bus Functional Model for MPSoC
I. Petkov, P. Amblard, A. Jerraya (TIMA Laboratory), M.
Hristov (ECAD Laboratory, Sofia)
Modeling and Prototyping of Communication Systems
using Java: a Case Study
L. Indrusiak, R. Prudencio, M. Glesner (TU Darmstadt)
A Rapid System Prototyping Platform for Error Control
Coding in Optical CDMA Networks
M. Irman, J. Bajcsy (McGill University)
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| 15:50 |
Closing |
| 16:10 |
End of sessions for day III |
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