Registration

Opening Welcome

Keynote Speech
(Session Chair: W. Hardt)

Formal Verification, Prof. Dr. Rolf Drechsler, Univ. Bremen

Break

Session 1: Formal Specification and Verification
(Session Chair: D. Buchs)

1. Formal Specification and Verification of Embedded System with Shared Resources
   K. S. Bang, J. Y. Choi (Korea University), S. H. Jang (KOREA Air-Force)
2. Automated Hardware Synthesis from Formal Specification
   D. Greaves (University of Cambridge)
3. ASET: A Formal Model for System Emulation and Verification
   S. Bhattacharya, J. Bhattacharyya, A. Chaudhuri (Jadavpur University, India)
4. TLCharts: Armor-plating Harel Statecharts with Temporal Logic
   D. Drusinsky, M. Shing (Naval Postgraduate School)

Lunch

Session 2: Co-Design Tools and Techniques
(Session Chair: F. Rousseau)

1. Improvement of Compiled Instruction Set Simulator by Increasing Flexibility and Reducing Compile Time
   M.K. Chung, C.M. Kyung (Korea Advanced Institute of Science and Technology)
2. Characterizing Power Consumption and Delay of Functional/Library Components for Hardware/Software Co-design of Embedded Systems
   A. Mohsen, R. Hofmann  (University of Erlangen)
3. Automatic Generation of a Simulation Compiler by HW/SW Co-Design System
   H. Yanagisawa, M. Uehara, H. Mori (Toyo University)

Session 3: Poster presentation
(Session Chair: P. Young)

1. Co-validation Environment for Memory Card Compatibility Test: A Case Study
   C. Park, S. Cho, H. Park, J. Lee (SAMSUNG Electronics Co.)
2. Network Interface Generation for MPSOC: From Communication Service Requirements to RTL Implementation
   A. Grasset, F. Rousseau, A.A. Jerraya (TIMA)
3. Rapid Prototyping and Performance Analysis for CDMA2000
   M. De Nobili, R.W. Stewart (Strathclyde University), G.C. Freeland (EnTegra Ltd.)
4. State Pruning for Test Vector Generation for a Multiprocessor Cache Coherence Protocol
   Y. Chen, D. Lilja (University of Minnesota), D. Abts (Cray Inc.)

Break + Poster session

Session 4: System Modeling and Architecture (I)
(Session Chair: W. Hardt)

1. An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor SoC
   F. Gharsalli, A. Baghdadi, M. Bonaci, G. Majauskas, W. Cesario, A. Jerraya (TIMA)
2. Automatic Building of Executable Models from Abstract SoC Architectures Made of Heterogeneous Subsystems
   A. Sarmento, W. Cesario, A. Jerraya (TIMA)
3. Hardware-Assisted Simulation and Evaluation of IP Cores Using FPGA-based Rapid Prototyping Boards
   R. Siripokarpirom, F. Mayer-Lindenberg  (Technical University Hamburg-Harburg)
4. High Level Synthesis Methodology from C to FPGA Used for a Network Protocol Communication
   M. Diaby, M. Tuna, J. Desbarbieux, F. Wajsburt  (Université Pierre et Marie Curie - LIP6)

Registration

Keynote Speech
(session Chair: D. Buchs)

Domain Driven Software Development - A Wolrd of transformations, Dr. Shane Sendall, IBM

Break

Session 5: Methodologies and tools
(Session Chair: B. Michael)

1. Automatic Generation of Virtual Prototypes
   P. Belanovic, M. Holzer, B. Knerr, G. Sauzon, M. Rupp (TU Wien)
2. Rapid Software Prototyping Using Visual Language Techniques
   K. Zhang, G.L. Song, J. Kong (University of Texas at Dallas)
3. Generation of Distributed Programs in their Target Execution Environment
   F. Gilliers (LIP6/Sagem), F. Kordon (Université Pierre et Marie Curie - LIP6), J. Velu (Sagem)
4. Approaching Interoperability from the Bottom-up: A Lattice Structure for the Object-Oriented Method for Interoperability (OOMI)
   G. Lawler (US Navy - Supervisor of Ship Building), P. Young (US Naval Academy)

Lunch + RSP program Committee Meeting

Session 6: FPGA-Based Systems (I)
(Session Chair: A. Dollas)

1. Self-Reconfiguration of Communication Interfaces
   A. Meisel, M. Visarius, W. Hardt (Chemnitz University of Technology), S. Ihmor (University Paderborn)
2. Multi-User FPGA Co-Simulation Over TCP/IP
   D. Denning (Institute of System Level Integration), J. Irvine (Strathclyde University), D. Stark (Nallatech), M. Devlin (Nallatech)
3. SystemC Model of a MPEG-2 DVB-T Bit-rate Measurement Architecture for FPGA Implementation
   C. Tanougast, Y. Berviller, C. Mannino, H. Rabah, M. Janiaut and S. Weber  (L.I.E.N - Université HENRI POINCARE Nancy 1)
4. Rapid Prototyping of a Co-Designed Java Virtual Machine
   K. Kent, H. Ma (University of New Brunswick), M. Serra (University of Victoria)

Break

Discussion Session
(Session Chair: F. Kordon)

Banquet Dinner

Registration

Session 7: Case Studies
(Session Chair: F. Rousseau)

1. Transmission Systems Prototyping based on Stateflow/Simulink Models
   N. Papandreou, M.Varsamou (Computer Technology Institute), T. Antonakopoulos  (University of Patras)
2. A Case Study on Rapid Prototyping of Hardware Systems: the Effect of CAD Tool Capabilities, Design Flows, and Design Styles
   A. Dollas, D. Theodoropoulos, K. Papademetriou, E. Sotiriades, I. Koides, G. Vernardos (Technical University of Crete)
3. Rapid Prototyping of an Integrated Testing and Debugging Unit
   R. Ludewig, T. Hollstein, F. Schütz, M. Glesner (Darmstadt University of Technology)
4. Transaction-level Prototyping of a UMTS Outer-modem for System-on-chip Validation and Architecture Exploration
   P. Martinelli, A. Wellig, J. Zory (STMicroelectronics N.V.)

Break

Session 8: System Modeling and Architecture (II)
(Session Chair: V. Olive)

1. Modeling and Simulation of System-of-Systems Timing Constraints with UML-RT and OMNet++
   J.B. Michael, M. Shing, M. Miklaski, J. Babbitt (Naval Postgraduate School)
2. Abstract RTOS Modeling for Embedded Systems
   F. Hessel, V. Rosa, I. Reis, R. Planer (PUCRS - BRAZIL), C. Marcon, A. Susin (UFRGS - BRAZIL)
3. Architecture Exploration of a Large Scale System
   S. Alliot (ASTRON Netherlands Foundation for Radio Astronomy), E. Deprettere (LIACS Leiden University)

Lunch

Session 9: FPGA-Based Systems (II)
(Session Chair: M. Shing)

1. Real Time Prototyping of Broadband Wireless LAN Systems
   M. Wouters, P. Van Wesemael, R. Vandebriel, A. Dewilde, M. Libois (IMEC vzw)
2. Implementation of a Channel Equalizer for OFDM WLANs
   M. Serra, P. Puig (Universitat de Vic), J. Bordoll (Universitat Autònoma de Barcelona)
3. Prototyping with a Bio-inspired Reconfigurable Chip
   Y. Thoma, D. Roggen, E. Sanchez (EPFL), J.-M. Moreno (UPC Barcelona)

Wrap-up & Closing