RSP'2002
Final Program

July 1-3, 2002
Darmstadt, Germany

 

Presentation kit (for authors)

Remarks

You will find the RSP'2002 program and, when autorization was provided, the slides presented there (in PowerPoint or pdf format according to what we had). Picture of speakers is also available when it was possible to relate pictures to a name (sorry, we do not know everybody;-)

Program at a glance

Detailed program

Monday July 1st

07:30 

Registration

08:30 

Opening Session

09:00 

Keynote Speech
(Session Chair: F. Kordon, LIP6 - Univ. paris 6)

  • "Market estimation for system prototyping EDA segment", Marco Pavesi (System Prototyping laboratory- Italtel)
    •

    10:00

    Break

    10:30

    Session 1: Prototyping Micro Architectures
    (Session Chair: M. Glesner - TU-Darmstadt)

    1. "Design of application specific CISC using PEAS-III", A. Kitajima (Osaka Electro-Communication University), T. Sasaki, Y. Takeuchi, N. Imai (Osaka University)
    2. "Rapid Prototyping of FPGA based Floating Point DSP Systems", C.H. Ho, M.P. Leong, P.H.W. Leong (Chinese Univ. of Hong Kong), J. Becker, M. Glesner (Univ. Karlsruhe)
    3. "Prototyping of Fuzzy Logic-Based Controllers Using Standard FPGA Development Boards", S. Sànchez-Solano R. Senhadji (Centro Nacional de Microelectrònica - Sevilla) A. Cabrera (Facultad de Ingenierìa Elèctrica - Cuba) I. Baturone C. J. Jimènez A. Barriga (Instituto de Microelectrònica de Sevilla)

    12:00

    Lunch

    13:30

    Session 2: Case Studies and Applications
    (Session Chair: W. Hardt - Univ. Paderborn)

    1. "A flexible H.263 video coder prototype based on FPGA", M. Garrido González, C. Sanz Alvaro, M. Jiménez Davia (EUIT Telecomunicacion-UPM) J. Meneses Chaus (ETSI Telecomunicacion-UPM)
    2. "Prototyping of A High Performance Generic Viterbi Decoder", A. Mohammad Obeid, A. Garcia Ortiz, R. Ludewig, M. Glesner (Institute for Microelectronic Systems, TU-Darmstadt)
    3. "On the Rapid Prototyping of Equalizers for OFDM Systems", T. Pionteck, N. Toender, L. D. Kabulepa (Darmstadt University of Technology) T. Kella (Infineon Technologies AG) M. Glesner (Darmstadt University of Technology)
    4. "Prototyping Ethernet in the First Mile on Point to Point Copper", M. Beck, E. Borghs, J. Jacobs, A. Mihanta, T. Pollet, P. Vandaele (Alcatel)

    15:30

    Break

    16:00

    Session 3: Mapping to FPGAs
    (Session Chair: R. Hartenstein, Univ. Kaiserslautern)

    1. "Benefits of Macro-based Multi-FPGA Partitioning for Video Processing Applications", J. Martín-Langerwerf, C. Reuter, H. Kropp, P. Pirsch (Univ. Hannover, IMS-AS)
    2. "Hybrid Multi-FPGA Board Evaluation by limiting multi-hop routing", S. Chandra Jain, A. Kumar (IIT, Delhi) S. Kumar (Univ. of Jonkoping, Sweden)
    18:00 Welcome Reception

     

    Tuesday July 2

    08:30 

    Keynote Speech
    (Session Chair: J. Henkel, NEC-Labs    )

    "FPGA's Rapidly Bridging Worlds", Yankin Tanurhan (Senior Director Actel)

    09:30

    Break

    10:00

    Session 4: Reconfigurable Software
    (Session Chair: Luqi, Naval Postgraduate School )

    1. "Rapid Prototyping of Transition Management Code for Reconfigurable Control Systems", M. Guler, N. Kejriwal, L. Wills, S. Clements, B. Heck, G. Vachtsevanos, Georgia Institute of Technology
    2. "Reconfigurable Hardware Control Software", C. Hinkelbein, A. Kugel, R. Maenner, M. Mueller, Mannheim University
    3. "Interfacing Software Libraries from Non-deterministic Prototypes", S. Chachkov, D. Buchs (LGL-EPFL)
    4. "Validating object-oriented prototype of real-time systems with timed automata", G. Shu, C. Li, Q. Wang, M. Li (Institute of Software ,Chinese Academy of Sciences)

    12:00

    Lunch

    13:30

    Session 5: High-level Modeling Issues
    (Session Chair: J. Becker, ITIV, Univ. Karlsruhe)

    1. "From Object-Oriented Modeling to Code Generation for Rapid Prototyping of Embedded Electronic Systems", M. Kühl, C. Reichmann, I. Prötel, K. D. Müller-Glaser (ITIV / Uni Karlsruhe)
    2. "System Prototyping by Integration of Reconfigurable Hardware into a Heterogeneous System Model", K. Buchenrieder, U. Nageldinger, A. Pyttel, A. Sedlmeier, (Infineon Technologies AG)
    3. "ISA based system design language in HW/SW co-design environment", H. Yanagisawa, M. Uehara, H. Mori (Toyo University)

    15:00

    Break

    15:30

    Session 6: New Synthesis and Estimation Approaches
    (Session Chair: K. Müller-Glaser, ITIV, Univ. Karlsruhe)

    1. "System-Level Co-Synthesis of Dataflow Dominated Applications on Programmable Dataflow Architectures", M. Véstias, H. Neto (INESC-ID/IST)
    2. "Power Estimation based on Transition Activity Analysis with an Architecture Precise Rapid Prototyping System", R. Ludewig, A. Garcia Ortiz, T. Murgan, M. Glesner (Darmstadt University of Technology)

    16:30

    Disscussion Session (animated by K. Müller-Glaser, ITIV, Univ. Karlsruhe)
    19:00 Conference Banquet

     

    Wednesday July 3

    08:30 

    Keynote Speech
    (Session Chair: M. Glesner, TU-Darmstadt    )

    "SoC Development Challenges", Rainer Kress (Infineon Technologies)

    09:30

    Break

    10:00

    Industrial Session
    (Session Chair: R. Ludevig, TU-Darmstadt)

    1. "Early design evaluation in hardware and system prototyping for concurrent hardware/software validation in one environment", U. Knipping - Aptix
    2. "The Common Problems with Rapid Prototyping (and solving them with Certify)", D. Amos - Synplicity
    3. "Advantages in commercial programmable backplanes thanks to pass-transistor technology", M. Ferloni - Italtel

    12:00

    Lunch

    13:30

    Session 7: Tools and Framework for Supporting RSP
    (Session Chair: V. Berzins - Naval Postgraduate School)

    1. "Framework for validation, test and analysis of real-time scheduling algorithms and scheduler implementations", F. Golatowski, J. Hildebrandt, J. Blumenthal, D. Timmermann (University of Rostock)
    2. "A Rapid Prototyping Environment for Distributed Reconfigurable Systems", C. Bobda (Paderborn University and Heinz Nixdorf Institute) N. Steenbock (Paderborn University and Heinz Nixdorf Institute)
    3. "RAPIDO: A Modular, Multi-Board, Heterogeneous Multi-Processor, PCI Bus Based Prototyping Framework for the Validation of SoC VLSI Designs", N. Busa, G. Alkadi (Philips Research Laboratories, Eindhoven) M. Verberne (Philips Semiconductor, System Labs, Eindhoven) R. Peset Llopis S. Ramanathan (Philips Research Laboratories, Eindhoven)
    4. "PICARD: Platform Concepts for Prototyping and Demonstration of High Speed Communication Systems", M. Wouters, T. Huybrechts, S. De Rore, S. Sanders, E. Umans , J. David (Imec vzw)
    15:30 Closing Session


    Last Modified: 03/26/2006 by F.Kordon on behalf of the program committee.