RSP'2000
Final Program

June 21-23, 2000
Hosted by l'Université Pierre & Marie Curie

 

Remarks

You will find the RSP'2000 program and, when autorization was provided, the slides presented there (in PowerPoint or pdf format according to what we had). Picture of speakers is also available when it was possible to relate pictures to a name (sorry, we do not know everybody;-)

Program at a glance

Wednesday June 21st

08:30 

Registration

09:00 

Opening Remarks (F. Kordon, Luqi)

09:30 

Keynote Speech

  • M. DaBose, "Senior Reasearch Engineers, Advance Program Research and Development", Raytheon Missile Systems
    •

    10:20

    Break

    10:45

    Session 1: Codesign methodologies
    (Session Chair: R. Lauvereins - K.U. Leuven)

    1. A Methodology for Implementing Medium Access Protocols Using a General Parameterized Architecture, M. Iliopoulos & T. Antonakopoulos (Univ. of Patras)
    2. Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems, A. Baghdadi, N-E. Zergainoh, W. Cesario, A.A. Jerraya (TIMA Laboratory) & T. Roudier (Arexsys, R&D center)
    3. Efficient Modeling of Preemption in a Virtual Prototype, Johan Cockx (IMEC)
    4. Combining Virtual Benchmarking with Rapid System Prototyping for Real-Time Embedded Multiprocessor Signal Processing System Codesign, R. Janka & L. Wills (Georgia Institute of Technology)

    12:25

    Buffet lunch (21st floor, central tower of the campus)

    13:55

    Session 2: Software methodologies
    (Session Chair: D. Buchs - Swiss Federal Institute of Technology)

    1. A Risk Assessment Model for Software Prototyping Projects, J-C. Nogueira, Luqi & S. Bhattacharya (Naval Postgraduate School)
    2. Processor Models for retargetable tools, R. Moona (IIT Kanpur)
    3. MODUS: Integrated Behavior-Oriented Model for Rapid Prototyping, Y. Gonzalez Arechavala & F. de Cuadra Garcia (Inst. de Investigacion Tech - Univ. Pontificia Comillas)
    4. Equivalence Checking of Two Statechart Specifications, M-H. Park, K_S. Bang, J-Y. Choi (KOREA University) & I. Kang (Soongsil Univ.)
    5. Intuitive Design of Complex Real-Time Control Systems, M. Dimmler (European Southern Observatory) & Y. Piguet (K-Team S.A.)

    15:00

    Break

    15:25

    Session 3: Tools
    (Session Chair: M. Glesner - Darmstadt Univ. of Technology)

    1. A Comprehensive Prototyping-Platform for Hardware-Software Codesign, A. Koch (Tech. Univ. Braunschweig)
    2. Cycle-true Simulation of the ST10 microcontroller, L. Gauthier & Ahmed Amine Jerraya (TIMA laboratory)
    3. Hardware/Software Co-Design of a Java Virtual Machine, K. Kent & M. Serra (Univ. of Victoria)
    4. Emulator environment based on an FPGA prototyping board, K-S. Oh, S-Y. Yoon & S-I. Chae (Seoul National Univ.)

    18:30

    Informal visit of the Quartier Latin

    19:30

    Evening free: music fair in Paris

    Thursday June 22nd

    08:30

    Keynote Speech

  • N. Mouawad, "The RAD experience: Lessons learned", S.A.I.C.
    •

    09:20

    Session 4: Real time systems
    (Session Chair: D. Lange - US Navy)

    1. Quasi-static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems, B. Bhattacharya & S. Bhattacharyya (University of Maryland)
    2. A design methodology for Hardware Prototyping of integrated AC drive control: Application to Direct Torque Control of an induction machine, P. Poure, F. Aubepart & F. Brun (LEPSI - IN2P3/CNRS-ULP)

    10:10

    Break

    10:35

    Session 5: Hardware methodologies
    (Session Chair: P. Young - Naval Postgraduate School)

    1. Speeding up hardware prototyping by incremental Simulation/Emulation, N. Canellas (Univ. Rovira i Virgili) & J. M. Moreno (Univ. Politcnica de Catalunya)
    2. Mapping a High-Speed Wireless Communication Function to the Reconfigurable J-Platform, V. Jain (Univ. of South Florida)
    3. A Prototype of an AAL for High Bit Rate Real-time Data Transmission System over ATM Networks Using a RSE CODEC, D. Eilers, R. Knorr, G. Kerner, A. Plankl & A. Voglgsang (Fraunhofer Institute for Communication Systems)
    4. The FLYSIG Prototyping Approach, W. Hardt, B. Kleinjohann & A. Rettberg (Lab Siemens AG & University Paderborn)

    12:15

    Lunch (restaurant)

    13:45

    Session 6: Code Generation
    (Session Chair: N. Mouawad - S.A.I.C.)

    1. A Verilog to C Compiler, D. Greaves (Univ. of Cambridge)
    2. Using MetaScribe to prototype an UML to C++/Ada95 code generator, D. Regep & F. Kordon (LIP6 - Univ. Paris 6)
    3. An Evaluation of Code Generation Strategies Targeting Hardware for the Rapid Prototyping of SDL-Specifications, A. Muth, T. Kolloch & T. Maier-Komor (Tech. Univ. Muenchen)

    15:00

    Break

    15:25

    Session 7: Methodologies
    (Session Chair: M. Lemoine - ONERA/Cdt-DPRS)

    1. Integration and Evolution of Model-Based Tool Prototypes, A. Bredenfeld (GMD)
    2. Coprocessor Synthesis of Multirate System Using Static Scheduling Theory, R. Kamdem & A. Fonkoua (LIM)
    3. Automated Communication Synthesis for Architecture-precise Rapid Prototyping of Real-time Embedded Systems, F-M. Renner, J. Becker & M. Glesner (Darmstadt Univ. of Tech.)
    4. Simulation and Real-time Rapid Prototyping of flexible Systems-on-a-Chip for Future Mobile Communication Systems, J Becker, L. Kabulepa, F-M. Renner & M. Glesner (Darmstadt Univ. of Tech.)

    18:30

    The Louvre of Charles V (visit)

    20:00

    Conference Banquet

    Friday June 23rd

    08:30

    Keynote Speech

  • K. Mülller-Glaser, "Rapid System Prototyping of Embedded Systems - Really Rapid?", University of Karlsruhe
    •

    09:20

    Session 8: Reconfigurability in Hardware Systems
    (Session Chair: V. Jain - University of South Florida)

    1. Reconfigurable Instruction Set Processors: A Survey, F. Barat & R. Lauwereins (K.U.Leuven)
    2. Highly Configurable Control Board: a Tool and a Design Experience, E. de la Torre, T. Riesgo, J. Uceda (Univ. Politécnica de Madrid), E. Macip & M. Rizzi (INDRA DTD)

    10:10

    Break

    10:35

    Session 9: Hardware systems
    (Session Chair: K. Müller-Glaser - University of Karlsruhe)

    1. Power-Constrained Block-Test List Scheduling, V. Muresan, X. Wang (Dublin City Univ.), V. Muresan & M. Vladutiu (Politehnica Univ. of Timisoara)
    2. Adaptive FPGA Placement by Natural Optimisation, J. de Vicente (ETSIAN), J. Lanchares & R. Hermida (Univ. Complutense de Madrid)
    3. A Hardware Virtual Machine to Support Networked Reconfiguration, Y. Ha, H. De Man (IMEC-K.U.Leuven), P. Schaumont, M. Engels, S. Vernalde & F. Potargent (IMEC)
    4. FPGA Technology Snapshot : Current Devices and Design Tools, H. Krupnova & G. Saucier (CSI/INPG)

    12:15

    Lunch (restaurant)

    13:45

    Session 10: Industrial session
    (Session Chair: F. Kordon - Université Paris 6)

    1. " Designing a Home Alarm using the UML and implementing it using C++ and VxWorks", P-M. Potier (iLOGIX)
    2. "An example of UML model level Prototyping", P.A. Muller (Objexion)

    14:35

    Session 11: Embedded systems
    (Session Chair: M. DaBose - Raytheon Missile Systems )

    1. Hardware Accelerated Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams, U. Mayer & M. Glesner (Darmstadt Univ. of Tech.)
    2. Efficient Clock-Cycle Precise Simulation at Architecture Level in C++, G. Eggers & H. Zeidler (Univ. der Bundeswehr Hamburg)
    3. Embedded System Architecture Design Based on Real-Time Emulation, C. Nitsch (Univ. of Leipzig) , K. Weiss, T. Steckstor (FZI), W. Rosenstiel (FZI and Univ. of Tuebingen), U. Kebschull (Univ. of Leipzig)

    15:50

    Closing session

    16:20

    Break

    16:45

    End of the conference



    Last Modified: 03/26/2006 by F.Kordon on behalf of the program committee.